1 ps8945b 08/28/09 features ? 4 differential channel, 2:1 mux/demux ? pci express ? 2.0 performance, 5.0gbps ? pinout optimized for placement between two pcie slots ? bi-directional operation ? low bit-to-bit skew, 5ps max ? low crosstalk: -26db@5 ghz ? low off isolation: -20db@5 ghz ? v dd operating range: +3.3v ? esd tolerance: 2kv hbm ? low channel-to-channel skew, 35ps max ? packaging (pb-free & green): ? 42-contact, tqfn (zh42) description pericom semiconductor?s pi3pcie2415 is an 8 to 4 differential channel multiplexer/demultiplexer switch. this solution can switch 2 full pci express ? 2.0, lanes to one of two locations. using a unique design technique, pericom has been able to minimize the impedance of the switch such that the attenuation observed through the switch is negligible. the unique design technique also offers a layout targeted for pci express signals, which minimizes the channel to channel skew as well as channel to channel crosstalk as required by the pci express speci cation. application routing of pcie ? 2.0, signals with low signal attenuation. block diagram pin description (top-side view) pi3pcie2415 3.3v, pci express ? 2.0, 2-lane, 2:1 mux/demux switch truth table function sel xiy to xoay l xiy to xoby h sel bi bi ai ai + + ? ? di di ci ci + + ? ? boa boa aoa aoa + + ? ? bob bob aob aob + + ? ? doa doa coa coa + + ? ? dob dob cob cob + + ? ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 42 41 40 39 18 19 20 21 gnd v dd gnd v dd gnd v dd gnd v dd gnd ai+ ai- aob+ aob- bi+ bi- bob+ bob- v dd ci+ ci- cob+ cob- di+ di- dob+ dob- aoa+ aoa- gnd gnd v dd boa+ boa- v dd sel gnd coa+ coa- v dd gnd doa+ doa- gnd 09-0009
2 ps8945b 08/28/09 pi3pcie2415 3.3v, pci express ? 2.0, 2-lane, 2:1 mux/demux switch signal descriptions pin number pin name type description 1, 2 ai+, ai- differential input differential input pair from pcie signal source. signal is passed through to the aoa+, aoa- pin respectively when sel=0. signal is passed through to the aob+, aob- pin respectively when sel = 1. 37, 36 aoa+, aoa- differential pass-through input differential analog pass-through output. signal from ai+ and ai- is passed through aoa+ and aoa- respectively when sel=0. 3, 4 aob+, aob- differential pass-through input differential analog pass-through output. signal from ai+ and ai- is passed through aoa+ and aoa- respectively when sel=1. 5, 6 bi+, bi- differential input differential input pair from pcie signal source. signal is passed through to the boa+, boa- pin respectively when sel=0. signal is passed through to the bob+, bob- pin respectively when sel = 1. 33, 32 boa+, boa- differential pass-through input differential analog pass-through output. signal from bi+ and bi- is passed through boa+ and boa- respectively when sel=0. 7, 8 bob+, bob- differential pass-through input differential analog pass-through output. signal from bi+ and bi- is passed through bob+ and bob- respectively when sel=1. 10, 11 ci+, ci- differential input differential input pair from pcie signal source. signal is passed through the coa+, coa- pin respectively when sel=0. signal is passed through to the cob+, cob- pin respectively when sel = 1. 28, 27 coa+, coa- differential pass-through input differential analog pass-through output. signal from ci+ and ci- is passed through coa+, coa- pin respectively when sel = 0. 12, 13 cob+, cob- differential pass-through input differential analog pass-through output. signal from ci+ and ci- is passed through cob+, cob- pin respectively when sel = 1. 14, 15 di+, di- differential input differential input pair from pcie signal source. signal is passed through the doa+, doa- pin respectively when sel=0. signal is passed through to the dob+, dob- pin respectively when sel = 1. 24, 23 doa+, doa- differential pass-through input differential analog pass-through output. signal from di+ and di- is passed through doa+, doa- pin respectively when sel = 0. 16, 17 dob+, dob- differential pass-through input differential analog pass-through output. signal from di+ and di- is passed through dob+, dob- pin respectively when sel = 1. 18, 20, 22, 25, 29, 35, 38, 40, 42 gnd ground input ground 30 sel 3.6v tolerant low-voltage single-ended input sel controls the mux through a ow-through latch. 9, 19, 21, 26, 31, 34, 39, 41 v dd power supply power, 3.3v 10% 09-0009
3 ps8945b 08/28/09 pi3pcie2415 3.3v, pci express ? 2.0, 2-lane, 2:1 mux/demux switch recommended operating conditions symbol parameter conditions min typ max units v dd 3.3v power supply 3.0 3.3 3.6 v i dd total current from v dd 3.3v supply 0 2.5 ma t case case temperature range for operation within spec. -40 85 celsius electrical characteristics storage temperature ....................................................?65c to +150c supply voltage to ground potential ................................?0.5v to +4.6v dc input voltage .............................................................. ?0.5v to v dd dc output current ....................................................................... 120ma power dissipation ........................................................................... 0.5w note: stresses greater than those listed under max i mum rat ings may cause permanent damage to the de vice. this is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i ca tion is not implied. expo- sure to absolute max i mum rating con di tions for extended periods may affect re li abil i ty. maximum ratings (above which useful life may be impaired. for user guide lines, not tested.) dc electrical characteristics (t a = ?40c to +85c, v dd = 3.3v 10%) parameter description test conditions min typ (1) max units v ih-sel (2) input high level, sel input 2.0 3.6 v v il-sel (2) input low level, sel input 0 0.8 v i in_sel (2) input leakage current, sel input measured with input at v ih-sel max and v il-sel min ?10 10 ua r on on resistance v dd = min., v in = 1.3v, i in = 40ma 12 ohm c on on channel capacitance v in = 0, v dd = 3.3v 2.0 pf note: 1. typical values are at v dd = 3.3v, t a = 25c ambient and maximum loading. dynamic electrical characteristics for xi, xoy parameter description test conditions min. typ. (1) max. units ddil differential insertion loss f=1.2ghz f=2.5ghz f=5.0ghz f=7.5ghz -1.5 -2.0 -5.0 -9.0 db ddil off differential off isolation f= 0 to 3.0ghz -20.0 ddrl differential return loss f= 0 to 2.8ghz f= 2.8 to 5.0ghz f= 5.0 to 7.5ghz -14.0 -8.0 -4.0 ddnext near end crosstalk f= 0 to 2.5ghz f= 2.5 to 5.0ghz f= 5.0 to 7.5ghz -32.0 -26.0 -20.0 09-0009
4 ps8945b 08/28/09 pi3pcie2415 3.3v, pci express ? 2.0, 2-lane, 2:1 mux/demux switch switching characteristics (t a = -40o to +85oc, v dd = 3.3v10%) parameter description test conditions min. typ. max. units t pzh , t pzl line enable time - sel to xi, xoy see "test circuit for electrical characteristics" 0.5 12.0 ns t phz , t plz line disable time - sel to xi, xoy see "test circuit for electrical characteristics" 0.5 12.0 ns t b-b bit-to-bit skew within the same differential pair see "test circuit for electrical characteristics" 7ps t ch-ch channel-to-channel skew see "test circuit for electrical characteristics" 35 ps 5.0 gbps receive eye mask -3.5db with the switch 09-0009
5 ps8945b 08/28/09 pi3pcie2415 3.3v, pci express ? 2.0, 2-lane, 2:1 mux/demux switch differential insertion loss differential return loss 09-0009
6 ps8945b 08/28/09 pi3pcie2415 3.3v, pci express ? 2.0, 2-lane, 2:1 mux/demux switch differential off isolation differential crosstalk 09-0009
7 ps8945b 08/28/09 pi3pcie2415 3.3v, pci express ? 2.0, 2-lane, 2:1 mux/demux switch switch positions test switch t plz , t pzl 2 x v dd t phz , t pzh gnd prop delay open switching waveforms voltage waveforms enable and disable times t plz v dd /2 v dd /2 v dd v oh 0v v ol v dd/2 v dd/2 t phz t pzl t pzh output 1 output 2 v ol v oh sel v ol + 0.15v v oh ? 0.15v r t 4pf c l v dd v in v out 200-ohm 200-ohm 2 x v dd pulse generator d.u.t test circuit for electrical characteristics (1-5) notes: 1. c l = load capacitance: includes jig and probe capacitance. 2. r t = termination resistance: should be equal to z out of the pulse generator 3. output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. all input impulses are supplied by generators having the following characteristics: prr mhz, z o = 50, t r 2.5ns, t f 2.5ns. 5. the outputs are measured one at a time with one transition per measurement. + ? + ? balanced port1 dut + ? 50 50 + ? balanced port2 50 50 diff. near end xtalk test circuit + ? + ? balanced port1 balanced port2 dut + ? 50 50 diff. off isolation test circuit + ? + ? balanced port1 balanced port2 dut diff. insertion loss and return test circuit 09-0009
8 ps8945b 08/28/09 pi3pcie2415 3.3v, pci express ? 2.0, 2-lane, 2:1 mux/demux switch differential inputs/output characteristics for pcie ? 2.0 speeds symbol parameter min nom max units comments tbit unit interval 199.94 200.00 200.06 ps de ned by pcie 2.0 spec. v rx-diffp-p differential input peak-to- peak voltage tbd 1.200 v vrx-diffp-p = 2*|vrx-d+ - vrx-d-|. applies to in_s and rx_in signals. t rx-eye minimum eye width at in_d input pair. tbd tbit v cm-ac-pp ac peak common-mode input voltage 100 mv vcm-ac-pp = |vrx-d+ + vrx-d-|/2 - vrx-cm-dc. vrx-cm-dc = dc(avg) of |vrx-d++vrx-d-|/2 vcm-ac-pp includes all frequencies above 30khz. z rx-diff-dc dc differential input im- pedance 80 100 120 ?? rx dc differential mode impedance z rx-dc dc input impedance 40 50 60 ? required in_d+ as well as in_d- dc impedance (50 ?? 20% tolerance). includes mux resistance. v rx-bias rx input termination volt- age 0 2.0 v intended to limit power-up stress on pcie output buffers. applications information 09-0009
9 ps8945b 08/28/09 pi3pcie2415 3.3v, pci express ? 2.0, 2-lane, 2:1 mux/demux switch ordering information ordering code package code package description pi3pcie2415zhe zh pb-free & green, 42-contact tqfn notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com packaging mechanical: 42-contact tqfn (zh) description: 42-contact thin fine pitch quad flat no-lead (tqfn) package code: zh (zh42) document control #: pd-2035 revision: c date: 02/17/09 notes: 1. all dimensions are in millimeters, angles in degrees. 2. coplanarity applies to the exposed thermal pad as well as the terminals. 3. refer jedec mo-220 4. recommended land pattern is for reference only. 5. thermal pad soldering area 09-0116 all trademarks are property of their respective owners. 09-0009
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